This invention relates to high-speed serial interface (“HSSI”) circuitry, and more particularly to automatic calibration of the receiver portion of such circuitry.
High-speed serial data signalling is widely used for transmitting data between devices in electronic systems. As just one example, such signalling may be used to transmit data between several integrated circuit devices on a printed circuit board. Typical high-speed serial data rates are in the range between about 6 Gbps (giga-bits per second) and about 10 Gbps, but higher or lower data rates are also possible.
In many systems that use high-speed serial data signalling, the serial data signal is transmitted without an accompanying clock signal that can be used by the circuitry that receives the data signal to enable the receiver (“RX”) circuitry to know when to sample the received data signal in order to capture successive bits in the received signal. In such cases the RX circuitry may include so-called clock and data recovery (“CDR”) circuitry to make the sampling time determination. The received signal will also typically have been subject to some loss and/or distortion during transmission. In addition, the receiver circuit components that initially receive and process the incoming signal may not be perfect, and they may themselves tend to introduce further loss and/or distortion before passing the received signal on to downstream circuitry such as the above-mentioned CDR circuitry. Such loss and/or distortion increases the difficulty of accurately recovering data from the serial data signal at the receiver. This difficulty is further increased by such design objectives as reduced voltage or power of the transmitted signal, increased data rate of that signal, etc.